Bulk metal-oxide-semiconductor-field-effect-transistors (hereinafter “MOSFETs”) are typically fabricated in the top few micrometers of a silicon wafer having a total thickness of several hundred micrometers. As such, a majority of the parasitic effects in bulk MOSFETs are a result of the interaction between the fabricated transistors and the substrate.
Silicon-on-insulator (hereinafter “SOI”) MOSFETs typically include a silicon layer that is overlaid on an insulation layer made of, for example, silicon dioxide, that is overlaid on a silicon substrate. The insulation layer of silicon dioxide can be created by introducing oxygen onto a silicon wafer and then heating the wafer to oxidize the silicon, thereby creating a uniform buried layer of silicon dioxide. In SOI MOSFETs, the dielectric isolation of the devices due to the silicon dioxide insulation layer prevents the occurrence of a majority of the parasitic effects that are present in bulk MOSFETs.
The buried insulating silicon dioxide layer provides many advantages for SOI MOSFETs over bulk MOSFETs, such as, for example: lower junction capacitance resulting in improved device speed, isolation of neighboring devices preventing transistor “cross talk,” smaller junction area resulting in a lower leakage current, and better short-channel effects. As a result of the improved functionality of SOI MOSFETs, these transistors are more regularly used for system-on-chip (hereinafter “SoC”) applications that require the integration of analog, digital, mixed-signal, and/or RF circuits on one chip.
However, the performance of SOI MOSFETs is considerably different relative to bulk MOSFETs due to the existence of the insulating silicon dioxide layer underneath the top silicon, or device layer. In particular, the presence of the insulating silicon dioxide layer causes self-heating due to the significantly lower, about 100 times lower, thermal conductivity of silicon dioxide (κ=1.4 W/K-m) relative to that of bulk silicon at room temperature (κ=140 W/K-m). The self-heating of the insulating silicon dioxide layer can cause several adverse effects in SOI MOSFETs, such as, for example, degraded drive current due to the mobility reduction, and decreased transconductance and speed of the transistor. The self-heating effects become more significant as the density of the transistors fabricated on a single silicon chip is increased.
Silicon-on-diamond (hereinafter “SOD”) transistors can be used as an alternative to SOI transistors due to their improved self-heating characteristics. The inherent electrical insulating properties of diamond in combination with its relatively high thermal conductivity (κ=2000 W/K-m) make it a superb substitute for the insulating silicon dioxide. Due to the high thermal conductivity of diamond, the heat generated in the active silicon region of a SOD MOSFET spreads away from the junction and into the underlying substrate, die package, and heat sink. As such, SOD MOSFETs can operate at much higher power levels relative to SOI MOSFETs at the same junction temperature. Various measurements have shown that SOD MOSFETs can sustain a power density greater than ten times that of SOI MOSFETs.
However, fully-depleted SOD MOSFETs suffer from an increase in short-channel effects relative to SOI MOSFETs. One parameter used to determine short-channel effects is the drain induced barrier lowering (hereinafter “DIBL”) effect of transistors. DIBL is defined as the threshold voltage variation between low and high drain voltages.
Because insulating diamond or diamond-like carbon film has a larger dielectric permittivity than silicon dioxide, the drain fringing field penetration inside insulating diamond film is larger than that of silicon dioxide. As a result, DIBL increases in fully-depleted SOD MOSFETs in comparison with fully-depleted SOI MOSFETs. For example, a 22 nm Ultra Thin Body (hereinafter “UTB”) SOD MOSFET can have a 22% deterioration of DIBL in comparison with a UTB SOI MOSFET.
Thinning the insulation layer of fully-depleted SOD MOSFETs can improve DIBL. For example, using this method, the DIBL value of a 20 nm UTB SOD MOSFET and a 20 nm UTB SOI MOSFET would be similar if the silicon dioxide insulation layer thickness is reduced to 30 nm. However, a trade-off exists between DIBL and parasitic source-substrate (CS-Sub) and drain-substrate (CD-Sub) capacitances. In particular, as the silicon dioxide insulation layer thickness is reduced, the CS-Sub and CD-Sub increase, which adversely affects transistor performance and working frequency.
Therefore, there is a need to improve the short-channel effects of transistors without the disadvantages identified above. In particular, there is a need to provide fully-depleted SOD MOSFETs with improved DIBL characteristics while maintaining low parasitic CS-Sub and CD-Sub capacitances. Yet further still, there is a need for a method of manufacturing fully-depleted UTB SOD MOSFETs with improved DIBL characteristics.